This invention relates to electronic circuits, and more particularly, to method and structure for causing a plurality of clock signals to be disabled in a specific order and at required levels (i.e., logical 1 or logical 0). This invention has particular applications in integrated circuits, particularly CMOS logic devices wherein it is desired to minimize power consumption during a power down period without the inadvertent loss of synchronization and/or data during such power down periods and subsequent power up periods.
In many circuits, particularly CMOS devices which are utilized to minimize power consumption, the system clock is disabled during the power down period. In this manner, power consumption of the device is minimized during such power down period. However, heretofore, there has never been a structure or method for powering down a plurality of clocks in a single circuit in a predetermined order in such a fashion as to maintain each clock at a predetermined level associated with the power down cycle. Accordingly, it has heretofore not been possible to produce circuits utilizing a plurality of clocks, whether independent from each other or derived from each other, which can all be powered down in a desired sequence. Many circuits require a plurality of clocks in order to function properly. For example, a universal asynchronous receiver and transmitter (UART), (such as the NSC 858 and the NS 8250, manufactured and sold by National Semiconductor Corporation, the assignee of this invention) requires three basic clocks: the receiver clock; the transmitter clock; and the baud rate clock. A UART is a device which is capable of receiving and transmitting a serial data stream and converting such serial data stream to a parallel format for communication with a device capable of receiving data in a parallel format, such as a central processing unit.
For example, when the incoming and outgoing serial data channels are operating at the same serial data rate, the receiver clock and the transmitter clock may be one and the same and, if desired, derived from the baud rate clock. On the other hand, when the two serial data channels are operating at different serial data rates, the receiver clock and the transmitter clock must differ.